In the manufacture of integrated circuits there is a continuous demand for an increase in circuit density and complexity and a decrease in device dimensions. Requirements in terms of packaging and interconnection of devices are continuously on the rise. To facilitate the transfer of signals between circuit components externally-implemented connectors have been used such as bonded chips, flip chips, package substrates, ball grid array (BGA) substrates and pin grid array (PGA) substrates.
Among known interconnect technologies the flip chip (also called “Direct Chip Attach”) has the highest I/O density. In typical semiconductor fabrication a plurality of metal pads is formed on a wafer, serving as a connection for electrical input and electrical output. In the technology of flip-chip bonding, a solder material such as lead-tin solder is deposited on the metal pads of a chip. The chip is then inverted and the solder dots contacted with connectors of a circuit board. Re-melting the solder forms an interconnection. In contrast to conventional wire bonding however a large distance between individual input/output pads needs to be maintained to ensure the reliability of the device. Only a careful selection of the bump material can allow reducing bump dimensions and distances between individual bumps (for an overview see e.g. Wolf, M. J., et al., Nuclear Instruments and Methods in Physics Research A (2006) 565, 290-295). The conventional joining materials for flip chip packaging include eutectic Sn—Pb or high Pb solder alloys. Due to miniaturization requirements and the trend for green manufacturing, lead-free solders and adhesive flip chip technology (including isotropic, anisotropic and non-conductive adhesives) are gradually replacing the Pb-containing solders. For example, the Waste Electrical & Electronic Equipment (WEEE) Directive of the European Union has banned the use of lead from electrical and electronic components from Jul. 1, 2006. In other parts of the world, similar legislations are also expected to take effect sooner or later.
Between lead-free and solderless (adhesives) solutions, each has its own strengths and weaknesses. Lead-free soldering inherits the good alignment capability from soldering technology and has stronger joint strength; but its cost is higher than leaded solder. Another big concern over the use of lead-free solders is the long-term product reliability due to the different processing conditions. Soldering technology is also expected to hit the limit for down-scaling.
Adhesive joining is more tolerant to thermal mismatch strain and able to provide a finer pitch than a leaded joint, however it is prone to moisture attack. The moisture absorption may lead to loss of interconnection due to polymer relaxation and/or ionic migration (corrosion). Therefore, adhesive flip chips have been largely used for products in less stringent environments.
According to International Technology Roadmap for Semiconductors (Assembly and Packaging, International Technology Roadmap for Semiconductors, 2005), flip chip area array pitch (solder bumped) is going to decrease to 90 μm and flip chip on tape or film pitch will be as fine as 20 μm in 2010. Reduced pitch size (and joint height) means greater mismatch strain will be experienced by the joining material(s). To resolve such an issue, either a smaller die has to be used, which limits the I/O number in a chip, or more flexible joint materials has to be found. The adhesive flip chips, to certain extend, can provide flexibility but it suffers from the problem of long term relaxation and corrosion as discussed above. Another potential problem facing all existing packaging interconnect materials is the mass-migration induced failure such as electromigration and stress migration. The continued minimization will further increase the current density and stress gradient, thus higher risk of migration failure. Physical failure mechanisms and assessment techniques are heavily investigated in recent years.
In this regard carbon nanotubes have recently been introduced in electrical connections between semiconductor devices. For this purpose the carbon nanotubes are usually grown on the respective pads, e.g. by chemical vapor deposition in a suitable electrical field. In this regard international patent application WO 2006/048846 discloses conductive connections between components of an integrated circuit package via carbon nanotubes. The carbon nanotubes are grown on an interconnect to extend therefrom in a generally straight direction. The nanotubes are embedded in a connector and a metal pad are pressed together to form a bond. International patent application WO 2006/048847 discloses a tape adhesive type arrangement that is directionally conductive. The arrangement contains a tape base material extending laterally and having opposing upper and lower surfaces. Carbon nanotubes extend between the opposing surfaces in the general direction of the thickness of the tape.
U.S. Pat. No. 6,989,325 discloses an alternative deposition of carbon nanotubes by using carbon nanotubes that are functionalized with thiol groups at both ends. Thereby these carbon nanotubes, connect a metal pad, on which they stand vertically, to gold spheres forming a line-beam-shaped conductive bump. The gold spheres are in turn used to form a connection to a surface. Such an approach however has the draw-back that functionalization of carbon nanotubes can affect the mechanical stability and conductivity of the nanotubes.
All these approaches however require the use of elevated temperatures during the formation of the interconnect, either during growth of the carbon nanotubes or when joining gold spheres at the end of carbon nanotubes to a surface. These elevated temperatures may damage devices formed on a wafer by causing degradation of matter included therein during integrated circuit fabrication, for example matter with a low dielectric constant (low k materials). As an example, the lowest possible operating temperature for the chemical vapor deposition process is about 700° C. Such a temperature is often incompatible with integrated circuit processing requirements. Furthermore, there is a risk that under stress the formed forests of carbon nanotubes slip, thereby causing fractures, which reduce the conductivity of the interconnect.
It is therefore an object of the present invention to provide a method of forming an interconnect that avoids the drawbacks or shortcomings in the formation of the above bumps.